1. Field of the Invention
The invention relates to a phase lock loop, in particular to a circuit for accelerating frequency locking.
2. Description of the Related Art
Phase lock loop is a technology for synthesizing the frequency signal. FIG. 1 shows a conventional phase lock loop 100 receiving a low-frequency reference signal fREF for synthesizing a high-frequency output signal fVCO. The frequency divider 150 divides the output signal fVCO by a frequency division ratio N, and feedbacks a divided result fDIV to an input terminal of the phase lock loop 100. At the input terminal of the phase lock loop 100, a phase frequency detector 110 compares the phase of the reference signal fREF with the phase of the divided result fDIV, and generates a pull-up signal #U and a pull-down signal #D according to phase difference between the reference signal fREF and the divided result fDIV. For example, when the reference signal fREF leads the divided result fDIV, the phase frequency divider 110 outputs the pull-up signal #U. On the contrary, when the reference signal fREF lags the divided result fDIV, the phase frequency divider 110 outputs the pull-down signal #D. A charge pump 120 is coupled to the phase frequency detector 110, and converts the pull-up signal #U and the pull-down signal #D into a driving current iP. The driving current iP then passes through a low-pass filter 130 consisting of a resistor RA and two capacitors CA and CB, and is transformed into a driving voltage Vtune used for adjusting a voltage-control oscillator (VCO) 140. Eventually, the voltage-control oscillator 140 generates the output signal fVCO according to the driving current Vtune.
The phase lock loop (PLL) 100 forms a feedback mechanism. The driving voltage Vtune generated by the VCO 140 usually swings for a period of time, and converges slowly to a target driving voltage in frequency tracking process. The period of time is also referred to as a locking time. When the frequency of the output signal fVCO is not locked, a loop bandwidth determines the change rate of the driving voltage Vtune. If the loop bandwidth is wide, the driving voltage Vtune converges rapidly, but the phase lock loop is susceptible to noise. On the contrary, if the loop bandwidth is narrow, the driving voltage Vtune converges slowly, but it takes a longer time. In order to meet the demands of the rapid frequency hopping function and low phase noise for a wireless communication system in a conventional phase lock loop, rapid frequency locking is facilitated by increasing the current of the charge pump and decreasing the resistor RA of the low-pass filter to widen the loop bandwidth when the frequency is not be locked. Additionally, the current of the charge pump is decreased and the resistor RA of the low-pass filter is increased to narrow the loop bandwidth when the frequency is locked. However, in the rapid frequency locking process the switching of the loop bandwidth between the above two modes readily causes signal perturbation of the driving voltage Vtune that controls the VCO 140. For example, because the loop bandwidth is suddenly changed from a wider one to a narrower one, the resistor RA of the filter is switched to high resistance. However, the current flowing through the resistor is still very large, which equals to a high voltage drop across the resistor RA. As a result, it forms a voltage step for the output signal of the low-pass filter 130 (i.e. the driving voltage Vtune). The voltage step makes the phase lock loop depart from the locked frequency, and therefore the phase lock loop needs to be tracked again. Because the loop bandwidth has already switched to the narrower one at this moment, it takes a longer time to track the phase of the phase lock loop. The phenomenon does not satisfy the original purpose of rapid frequency locking. This phenomenon becomes worse for the fractional-N type frequency synthesizer. Therefore, a more rapid and stable phase lock loop is required.